Yilei Li

Research Scientist

I obtained my PhD in Electrical Engineering from UCLA in 2016, focusing on hardware-aware algorithm design for next-generation intra-/inter-chip interconnections. Afterwards I have been working with several AI chip projects, including low-power AI accelerator IP for embedded applications and high-throughput AI accelerator chip for edge compute.

Currently I am working on highly efficient model/hardware co-design for next-generation smart devices.


Efficient model design, model/hardware co-design